Apparatus and method for measuring conductivity

ABSTRACT

An improved apparatus for measuring conductivity or resistivity compensates for series capacitance and parallel capacitance. A sine wave excitation potential is applied to the series combination of a reference resistance and a conductivity cell. The voltages across the reference resistance and the cell are sampled. To compensate for series capacitance, both sampled voltages are synchronously rectified with respect to the phase of the sampled reference resistance voltage. To compensate for parallel capacitance, both sampled voltages are synchronously rectified with respect to the phase of the sampled cell voltage. The rectified voltages are integrated and the cell conductivity or resistivity is calculated from the product of the reference resistance and the ratio of the integrated voltages.

This application claims benefit of 60/027,327, filed Oct. 3, 1996, andthis application is a 371 of PCT/US97/17237, filed Sep. 25, 1997.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an improved apparatus and method for measuringelectrical conductivity or resistivity in liquids, and moreparticularly, it relates to a conductivity measuring apparatus having aphase-synchronous rectifier and integrator for accurately measuringelectrical conductivity in the presence of parasitic capacitance.

2. Background of the Invention

The measurement of conductivity or resistivity is desired in a number ofapplications. For example, in the pharmaceutical industry, manyprocesses require the use of ultra-pure water. Conductivity measurementsyield an indication of ionic concentrations in water. Ultra-pure waterhas a conductivity below a given level. Conductivity measurements cantherefore be used to reliably and accurately determine the purity ofwater.

Another application where it is desirable to measure the conductivity ofa liquid is the determination of the concentration of total dissolvedsolids in water. For example, investigators desiring to determine thelevel of pollution in river water want to know the concentration oftotal dissolved solids in the water. The higher the concentration oftotal dissolved solids in the water, the higher the conductivity, orinversely, the lower the resistivity of the water.

The volume conductivity, or just “conductivity”, is defined as theconductance of one cubic centimeter of a liquid at a specifictemperature. Conductivity is typically measured in mhos/cm (/cm), orSiemens/cm (S/cm), and micro mhos/cm (μ/cm), or micro Siemens/cm(μS/cm). Ultra-pure water typically has a conductivity of 0.2 micromhos/cm or less. Volume resistivity (“resistivity”) is the inverse ofconductivity and is typically measured in ohm-cm (Ω-cm), or megohm-cm(MΩ-cm). Ultra-pure water typically has a resistivity of 5 megohms-cm orgreater.

Conductivity of a liquid is typically measured by immersing twoelectrodes contained in a conductivity cell in the liquid, applying anexcitation to the liquid, and measuring the resultant voltage v_(c)between the electrodes and the current i_(c) flowing through theelectrodes. Because a direct current (“DC”) excitation can cause ionspresent in the liquid to migrate to the electrodes, interfering with theconductivity measurement, an alternating current (“AC”) excitation ofsufficiently low amplitude and sufficiently high frequency is oftenused.

Measurements of conductivity and resistivity vary depending upon thecell used to make the measurements, the temperature of the liquid beingmeasured, and the concentration of ions or other electrically conductivematerial in the liquid. A cell with fixed dimensions and configurationis typically used. For a given fixed cell, a cell constant K may bedefined as a function of conductive cell surface area and conductivepath length For a cell with two flat parallel plates of area A andseparation distance L, the cell constant K is found to be the length Lof the conductive path between the electrodes, divided by the conductingarea A of the electrodes, so that K=L/A.

For a given cell, the conductivity and resistivity of a liquid are thengiven by $\begin{matrix}{{\sigma = \frac{{Ki}_{c}}{v_{c}}}{and}} & \text{(eq. 1)} \\{\rho = {\frac{1}{\sigma} = \frac{v_{c}}{{Ki}_{c}}}} & \text{(eq. 2)}\end{matrix}$

Where:

i_(c)=the electric current flowing between the cell electrodes, inAmperes,

v_(c)=the voltage across the cell electrodes, in Volts, and

K=the cell constant, in cm⁻¹.

The conductivity cell immersed in liquid may be electrically modeled asa resistor R_(c) with value equal to the resistivity ρ times the cellconstant K, such that

R _(c) =Kρ.  (eq.3)

However, accurate measurement of R_(c) is difficult when an ACexcitation is used due to capacitive effects of the cell, as well ascapacitive effects of the lead wires to the cell. At the interfacebetween each cell electrode and the liquid is a series capacitanceC_(S). Between each electrode is a capacitance in parallel with theresistance R_(c), represented by C_(p). Including the capacitiveeffects, the cell may be electrically modeled as a parallel capacitanceC_(p) in parallel with liquid resistance R_(c), both in seriesconnection with series capacitance C_(s), as shown in FIG. 1. Lead wirecabling capacitance (not shown) would appear as a capacitance inparallel across the circuit of FIG. 1.

The cell capacitances C_(p) and C_(s) exhibit impedances to an ACexcitation which vary inversely as a function of the excitationfrequency f (measured in cycles/second or Hertz). For a relatively lowfrequency f, the impedances of C_(p) and C_(S) can be quite large forfixed values of C_(p) and C_(s). For small values of R_(c), theimpedance of series capacitance C_(s) can be large compared to R_(c),thus giving rise to an erroneously large measured value for R_(c). Forlarge values of R_(c), the impedance of parallel capacitance C_(p) canbe small relative to R_(c), thus giving rise to erroneously smallmeasured values of R_(c).

For a relatively high excitation frequency f the impedances of C_(p) andC_(s) can be quite small for fixed values of C_(p) and C_(s). For smallvalues of R_(c), the impedance of series capacitance C_(s) can be largecompared to R_(c), thus giving rise to an erroneously large measuredvalue for R_(c). For large values of R_(c), the impedance of parallelcapacitance C_(p) can be small relative to R_(c), thus giving rise to anerroneously small measured value for R_(c).

In general, at a given frequency f and fixed C_(s) and C_(p), as theresistivity of a sampled liquid increases, the impedance due to seriescapacitance C_(s) can be ignored, while the impedance of parallelcapacitance C_(p) causes an erroneously small value for R_(c) to bemeasured. Conversely, as the resistivity of a sampled liquid decreases,the impedance due to parallel capacitance C_(p) can be ignored, whilethe impedance of series capacitance C_(s) causes an erroneously largevalue for R_(c) to be measured.

Thus, for large values of cell resistance R_(c), the measurement erroris largely due to the presence of parallel capacitance C_(p). For smallvalues of cell resistance R_(c), the primary source of measurement erroris due to the presence of series capacitance C_(s).

Various efforts to measure conductivity in the presence of capacitiveeffects are known in the prior art. An early method uses an ACconductance bridge, wherein different reactances are inserted into thearms of the bridge to compensate either or both C_(s) and C_(p). Whilethis method is effective, it is generally slow and not easily automated.

Another measurement technique uses square-wave excitation andcenter-sampling of the voltage waveform across the cell. The parallelcapacitance is charged to saturation during the first part of thesquare-wave cycle. The cell voltage is then sampled during a laterportion of the cycle during which the series capacitance is charging ina linear fashion. The value of the series capacitance can be determinedfrom the rate of charge of the capacitance and mathematically subtractedfrom the output based on the cell voltage to determine the cellresistance. This measurement technique suffers from the disadvantage ofrelying upon the use of a second-order polynomial to approximate theamount of measurement error. Thus, this prior art method does noteliminate the source of error itself, the voltage due to the seriescapacitance.

SUMMARY OF THE INVENTION

These disadvantages and others are met by means of the present inventionembodied in a circuit and method for measuring the conductivity sensedby a cell wherein the effects of series and parallel capacitanceinherent in cells are mined.

In the present invention, a periodic time-varying excitation is appliedacross a known reference resistance series-connected to a cell sensor.The voltages across the reference resistance and the cell sensor aresynchronously sampled with respect to a predetermined signal phase. Thesynchronous sampled voltages are then integrated with respect to apredetermined signal phase to provide DC values representative of theirRMS values. By sampling and integrating the signals synchronously,voltage components due to cell capacitance are substantially eliminated,leaving the voltage components due to cell resistance. The cellresistance is then found as a product of the reference resistance andthe ratio of the RMS value of the synchronous sampled cell signal to theRMS value of the synchronous sampled reference resistance voltage.

Therefore, it is one object of the invention to provide a measurement ofthe conductivity of liquids reliably and accurately, even when parasiticcell capacitances are present. This and other objects, features andadvantages of the present invention will be described in further detailin connection with preferred embodiments of the invention shown in theaccompanying drawings, wherein:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an electrical schematic of a conductivity cell immersed in aliquid;

FIG. 2 is an electrical schematic of a conductivity cell immersed in aliquid modeled as a parallel RC circuit;

FIG. 3 is an electrical schematic of a conductivity measuring circuitmodeled as a series circuit;

FIG. 4 is an electrical schematic of a conductivity measuring circuitmodeled as a parallel circuit;

FIG. 5 is a block diagram of a conductivity measuring circuit;

FIG. 6 is a set of electrical waveforms illustrating the operation of aconductivity measuring circuit;

FIGS. 7a, 7 b, and 7 c are a detailed circuit schematic diagram of apreferred embodiment of the invention; and

FIG. 8 is a block diagram of a conductivity meter incorporating thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As discussed above, the resistance of a liquid the conductivity of whichis desired is not an ideal resistance. As shown in FIG. 1, aconductivity cell immersed in a liquid may be modeled as a cellresistance R_(c) in parallel with a capacitance C_(p), both in serieswith a capacitance C_(s).

Series capacitance C_(s) is caused by liquid-electrode interfacecapacitance and is a function of the resistivity of the liquid undermeasurement and the available surface area of the cell electrodes.Values for series capacitance C_(s) typically range from as low as 0.1μF to in excess of 100 μF. For example, platinum electrodes plated withhighly porous platinum black generally have C_(s)>1 μF, whiletitanium-palladium electrodes may typically have C_(s)≈0.1 μF.

Parallel capacitance C_(p) is caused by interelectrode capacitance,which is a function of cell geometry and electrode separation distance,as well as lead wire cabling capacitance. Cabling capacitance candominate interelectrode capacitance by a factor often times or more.Values for C_(p) typically may vary from a low of 10 pF to a high of2500 pF.

For large values of resistance R_(c), the principal source ofmeasurement error is due to the presence of parallel capacitance C_(p)while measurement error due to the presence of series capacitance C_(s)may be ignored. For small values of resistance R_(c), the principalsource of measurement error is due to the presence of series capacitanceC_(s) while measurement error due to the presence of parallelcapacitance C_(p) may be ignored.

By way of illustration, assume typical values for C_(s) and C_(p) suchthat C_(s)=1 μF and C_(p)=600 pF. At a driving frequency f=70 Hz, C_(s)and C_(p) will exhibit reactances X_(s) and X_(p) given by$\begin{matrix}{x = \frac{1}{2\pi \quad {fC}}} & \text{(eq. 4)}\end{matrix}$

such that X_(c)=2.274 kΩ and X_(p)=3.789 MΩ. The measured cellresistance R_(m) will then be given by $\begin{matrix}{R_{m} = {{{{X_{s} + {X_{p}}}}R_{c}} = {X_{s} + {\frac{1}{\frac{1}{R_{c}} + \frac{1}{X_{p}}}.}}}} & \text{(eq. 5)}\end{matrix}$

For the given values, and a required degree of accuracy, a range ofvalues for which R_(m) exhibits the required degree of accuracy forR_(c) can be determined. In this example, for a required measurementaccuracy of ±0.25%, the range over which R_(c) may be accuratelymeasured extends from a low value of R_(c)≈89.18 kΩ to a high value ofR_(c)≈99.01 kΩ, with minimal error at R_(c)≈93.96 kΩ.

Now, assuming that R_(c) and X_(p) are much larger than X_(s)(R_(c)>>X_(s) and X_(p)>>X_(s)), the electrical model of FIG. 1 can beapproximated by the simple parallel circuit of R_(c) in parallel withC_(p), as shown in FIG. 2. Provided that some means can be used tosubstantially compensate the effect of the parallel capacitance C_(p),then the accuracy of the measurement of R_(c) is limited only by thepresence of C_(s). For example, the measured resistance R_(m) as givenabove reduces to

R _(m) =X _(s) +R _(c).  (eq. 6)

Thus, for a required accuracy of +0.25%, the range for R_(c) now extendsfrom a low value of R_(c)≈909.6 kΩ to an arbitrarily large value limitedonly by the sensitivity of the measurement apparatus. For these largevalues of R_(c), R_(c)≧400 X_(s), and X_(p)≧1600 X_(s), thus verifyingthe assumptions that R_(c)>>X_(s) and X_(p)>>X_(s) are valid. Therefore,large values of cell resistance can be accurately measured using aparallel capacitance model, provided that some means is used tosubstantially compensate the effects of parallel capacitance C_(p).

The inventor has observed that for the series model shown in FIG. 3,

v _(ab) =iR _(ref)  (eq. 7)

and

v _(bd) =v _(bc) +v _(cd) =iR _(c) +v _(cd).  (eq. 8)

If both sides of the equations are integrated, then

∫v _(ab) dt=R _(ref) ∫idt  (eq. 9)

and

∫v _(bd) dt=R _(c) ∫idt+∫v _(cd) dt.  (eq. 10)

Solving for ∫idt in eq. 9 and substituting the result in eq. 10, then$\begin{matrix}{{\int{v_{bd}{t}}} = {{\frac{R_{c}}{R_{ref}}{\int{v_{ab}{t}}}} + {\int{v_{cd}{{t}.}}}}} & \text{(eq. 11)}\end{matrix}$

For periodic time-varying excitation v_(cd), limits l₁, l₂ can be chosensuch that $\begin{matrix}{{\int_{l_{1}}^{l_{2}}{v_{cd}{t}}} = 0.} & \text{(eq. 12)}\end{matrix}$

By way of example, l₁ and l₂ may have values:${l_{1} = {- \frac{\pi}{2\omega}}},{l_{2} = \frac{\pi}{2\omega}}$

where ω is the angular frequency of the driving signal and the times l₁and l₂ are measured with reference to the instant of zero crossover forthe signal v_(cd). It will be observed that the voltage v_(cd) may notbe measured, but it is known to be 90 degrees out of phase with v_(ab).Therefore, the limits l₁ and l₂ may be set with respect to the peakvalue of v_(ab), in which case they are equal to zero-crossings ofv_(ab).

Then, substituting eq. 12 in eq. 11 and solving for R_(c)$\begin{matrix}{R_{c} = {R_{ref}{\frac{\int_{l_{1}}^{l_{2}}{v_{bd}{t}}}{\int_{l_{1}}^{l_{2}}{v_{ab}{t}}}.}}} & \text{(eq. 13)}\end{matrix}$

Thus, the unknown resistance R_(c) can be found by multiplying the valueof the reference resistance by the ratio of the integral of the sampledcell voltage to the integral of the sampled reference voltage. The valueof the unknown resistance R_(c) can thereby be found despite thepresence of unknown series capacitance C_(s). However, it should benoted that l₂−l₁ may not have a value of 2π/ω, because such a conditioncauses Equation 13 to become indeterminate.

Similarly, for the parallel capacitance model shown in FIG. 4, theinventor has observed that

v _(ab) =i ₁ R _(ref) =R _(ref)(i ₂ +i ₃)  (eq. 14)

and

v _(bc) =i ₂ R _(c).  (eq. 15)

Integrating both sides of equations 14 and 15 yields

∫v _(ab) dt=R _(ref) ∫i ₂ dt+R _(ref) ∫i ₃ dt  (eq. 16)

and

∫v _(bc) dt=R _(c) ∫i ₂ dt.  (eq. 17)

Solving eq. 17 for ∫i₂dt and substituting the result in eq. 16 gives$\begin{matrix}{{\int{v_{ab}{t}}} = {{\frac{R_{ref}}{R_{c}}{\int{v_{bc}{t}}}} + {R_{ref}{\int{i_{3}{{t}.}}}}}} & \text{(eq. 18)}\end{matrix}$

For a periodic time-varying excitation v_(ac), i₃ is also periodic andlimits l₃, l₄ can be chosen such that $\begin{matrix}{{\int_{l_{3}}^{l_{4}}{i_{3}{t}}} = 0.} & \text{(eq. 19)}\end{matrix}$

By way of example, l₃ and l₄ may have values:${l_{3} = {- \frac{\pi}{2\omega}}},{l_{4} = \frac{\pi}{2\omega}}$

where ω is the angular frequency of the driving signal and the times l₃and l₄ are measured with reference to the instant of zero crossover forthe signal i₃. It will be observed that the current i₃ may not bemeasured, but it is known to be 90 degrees out of phase with current i₂and voltage v_(bc). Therefore, the limits l₃ and l₄ may be set withrespect to the peak value of v_(bc), in which case they are equal tozero-crossings of v_(bc).

Substituting eq. 19 into eq. 18 and solving for R_(c) yields$\begin{matrix}{R_{c} = {R_{ref}{\frac{\int_{l_{3}}^{l_{4}}{v_{bc}{t}}}{\int_{l_{3}}^{l_{4}}{v_{ab}{t}}}.}}} & \text{(eq. 20)}\end{matrix}$

Note the similarity of eq. 20 to eq. 13. Thus, the unknown resistanceR_(c) can be found by multiplying the value of the reference resistanceR_(ref) by the ratio of the integral of the sampled cell voltage v_(bc)to the integral of the sampled reference voltage v_(ab). The value ofthe unknown resistance R_(c) can thereby be found despite the presenceof unknown parallel capacitance C_(p). However, it should be noted thatl₄−l₃ may not have a value of 2π/ω, because such a condition causesEquation 20 to become indeterminate.

It can be shown that the ratio of the integrals given in Equations 13and 20 is equal to the ratio of the peak voltages divided by the cosineof the phase angle between the two voltage signals being monitored.Thus, if the peak voltage ratio is determined and is divided by theratio of the integrals, it becomes possible to determine the phase angleand hence the value of the unknown capacitance.

Turning now to an examination of an apparatus which compensates forunknown capacitance when measuring unknown resistance, FIG. 5 shows asimplified block diagram of a circuit according to one embodiment of theinvention. A liquid (not shown), the conductivity of which is to bemeasured, is disposed between electrodes (not shown) in a cell 10.Connected to one electrode of the cell 10 is a reference resistance 12.A sinusoidal voltage driving source 14 is connected across the referenceresistance 12 and the cell 10 to form a series electrical circuit.

A sample signal select switch 16, controlled by a microprocessor 26, isconnected so as to be able to connect either the voltage across thereference resistance 12, or the voltage across the cell 10, dependingupon which signal voltage is to be sampled, to a synchronous rectifier18. A phase signal select switch 20, controlled by the microprocessor26, is connected so as to be able to connect either the voltage acrossthe reference resistance 12, or the voltage across the cell 10,depending upon which signal voltage is to be the input to azero-crossing detector 22.

The zero-crossing detector 22 provides a zero-crossing detect signal tothe synchronous rectifier 18 each time the input signal to thezero-crossing detector 22 passes through zero Volts. Preferably, thesynchronous rectifier 18 provides, at its output, in response to thezero-crossing detect signal, a non-inverted version of the sample signalat its input whenever the input voltage to the zero-crossing detector 22is positive. When the input voltage to the zero-crossing detector 22 isnegative, the synchronous rectifier 18 preferably provides at its outputan inverted version of the sample signal at its input. Alternatively,the polarity of the output from synchronous rectifier 18 may be reversedwithout affecting the conductivity measurement. Then, when the inputvoltage to zero-crossing detector 22 is positive, the output fromrectifier 18 is an inverted version of its input, while when the inputvoltage to detector 22 is negative, the output from rectifier 18 is anon-inverted version of its input.

The output of the synchronous rectifier 18 is provided to the input ofan integrator 24. The integrator 24 produces a DC output voltage whichis representative of the RMS value of the input voltage. The output ofthe integrator 24 is provided to the microprocessor 26 which calculatesthe value of the cell resistance by multiplying the value of thereference resistance 12 times the ratio of the integratedsynchronously-rectified sampled cell voltage to the integratedsynchronously-rectified sampled reference resistance voltage.

Thus, the zero-crossing detector 22 supplies the proper limits ofintegration so as to compensate for the effects of unknown capacitancepresent in combination with the unknown resistance being measured.

The operation of the synchronous rectifier 18 may be more clearlyunderstood by referring to the voltage waveforms shown in FIG. 6. Thewaveforms share a common vertical axis which represents voltage. Thehorizontal axes represent time. Voltage V_(D) represents the drivingvoltage from signal source 14. Voltage V_(R) represents the sampledvoltage from reference resistor 12. Voltage V_(C) represents the sampledcell voltage from cell 10. For the sake of clarity, all three voltagesV_(D), V_(C), and V_(R) are shown as having equal amplitude. Also, V_(R)is shown with a phase angle of 30 degrees with respect to V_(D), andV_(C) is shown with a phase angle of −30 degrees with respect to V_(D).

To illustrate the case where the resistivity is high and it is desiredto remove the effects of parallel capacitance, synchronous rectificationwith respect to cell voltage V_(C) is shown. Voltage V_(CR) is theoutput of the synchronous rectifier 18 when V_(C) is the input tosynchronous rectifier 18 and zero-crossing detector 22. The verticaldashed lines in FIG. 6 show the timing relationship of the voltagewaveforms with respect to the zero crossings of V_(C). As can be seen,V_(CR) is a full-wave rectified version of V_(C).

Voltage V_(RR) is the output of synchronous rectifier 18 when V_(R) isthe input to the synchronous rectifier 18 and V_(C) is the input to thezero-crossing detector 22. During the time between zero crossings ofV_(C) when V_(C) is positive, V_(RR) is a non-inverted version of V_(R).However, during the time between zero crossings of V_(C) when V_(C) isnegative, V_(RR) is an inverted version of V_(R). Thus, V_(R) issynchronously rectified with respect to V_(C).

Voltage INT_(R) represents the output of integrator 24 when the input isV_(RR). Voltage INT_(C) represents the output of integrator 24 when theinput is V_(CR). Because V_(CR) is always a non-negative voltage,INT_(C) steadily increases over time as additional cycles of V_(CR) areintegrated. Because V_(RR) may be negative, INT_(R) may show dips inamplitude at the zero crossings of V_(C). If V_(R) were exactly in phasewith V_(C), then V_(RR) would match V_(CR), and INT_(R) would matchINT_(C). At the other extreme, if V_(R) were exactly 90 degrees out ofphase with V_(C), then INT_(R) would dip to zero at the zero crossingsof V_(C).

Thus, while the in-phase portion of V_(R) due to current through thecell resistance integrates to some positive value, the 90 degreeout-of-phase portion of V_(R) due to current through the cell parallelcapacitance integrates to a zero value. For the case of series cellcapacitance, the same principles may be demonstrated by exchanging thevoltages and viewing V_(R) as the sampled cell voltage, V_(C) as thesampled reference resistance voltage, V_(RR) as the synchronouslyrectified cell voltage, V_(CR) as the synchronously rectified referencevoltage, INT_(R) as the integrated cell voltage, and INT_(C) as theintegrated reference voltage.

FIGS. 7a, 7 b, and 7 c show a preferred embodiment of the presentinvention. A programmable sine-wave generator 30 receives inputs fromthe microprocessor 26 (FIG. 5) and produces a sine-wave output of fixedamplitude. One such programmable sine-wave generator 30 is the MicroLinear ML2035, which is programmable from DC to 25 kHz. The sine-wavegenerator 30 provides a highly stable source of sine-wave excitation ata frequency determined by the inputs from the microprocessor.

The output of sine-wave generator 30 passes through series-limitingresistor 32 and DC-blocking capacitor 34 to resistor 36 and thenon-inverting input of op amp 38. Op amps 38 and 40, and resistors 42,44, and 46, buffer the sine-wave signal and provide sufficient currentto drive a primary winding 50 of isolation transformer 48. The sine-waveinput to isolation transformer 48 is inductively coupled to twosecondary windings 52 and 54 of the transformer 48.

The secondary windings 52, 54 are series-connected. Capacitors 56 and 58are series-connected across the output of secondary windings 52, 54. Thecommon tap of windings 52, 54 is connected to switch 60. The other tapof winding 52 is connected to switches 62 and 64. Range selectionsignals RANGE_1, RANGE_2, and RANGE_3, from the microprocessor 26 (FIG.5), pass through series-limiting resistors 66, 68, and 70, to switches60, 62, and 64, respectively. Reference resistors 72, 74, and 76 areconnected in series with one end of resistor 72 tied to ground. Theoutput of switch 60 is connected to the common tie point of resistors 72and 74. The output of switch 62 is connected to the common tie point ofresistors 74 and 76. The output of switch 64 is connected to the otherlead of resistor 76.

In response to range selection signals RANGE_1, RANGE_2 and RANGE_3,from the microprocessor 26 (FIG. 5), the switches 60, 62, 64 may beturned on or off. A low range selection signal turns a switch on while ahigh range selection signal turns a switch off. When turned on, theswitches 60, 62, 64 have very low resistance and couple the sine-wavesignal from one of the windings 52, 54 to the reference resistors 72,74, 76. When the switches 60, 62, 64 are off, they exhibit very highinput impedance to provide isolation between the inputs to the switches60, 62, 64 and the reference resistors 72, 74, 76. Switches which may beused for this purpose are Photo-MOS relay switches made by Aromat.Switches 62, 64 may be Aromat AQV210EA switches which typically exhibit10¹⁰Ω off resistance and 30-100Ω on resistance. Switch 60 may be anAromat AQV215A which typically exhibits 10⁸Ω off resistance and about 5Ωon resistance.

Resistors 72, 74, and 76 preferably are precision resistors that exhibitsuperior stability over time and a wide range of operating conditions.Values for resistors 72, 74, and 76 preferably are 10Ω, 1 kΩ, and 100kΩ. Preferably, resistor 72 will have the smallest value and resistor 76will have the largest value.

In operation, when the resistance being measured is small, RANGE_3 islow, RANGE_1 and RANGE_2 are high, switch 60 is on, switches 62 and 64are off, and sine-wave excitation is coupled from the common tie pointof windings 52 and 54 to the common tie point of resistors 72 and 74.When the resistance being measured is of some intermediate value,RANGE_2 is low, RANGE_1 and RANGE_3 are high, switch 62 is on, switches60 and 64 are off, and sine-wave excitation is coupled from winding 52to the common tie point of resistors 74 and 76. When the resistancebeing measured is large, RANGE_1 is low, RANGE_2 and RANGE_3 are high,switch 64 is on, switches 60 and 62 are off, and sine-wave excitation iscoupled from winding 52 to resistor 76.

Secondary winding 54 is further connected to cell 10 and resistor 78.Preferably, cell 10 is a four-wire, four-element cell. Alternatively,cell 10 may be a four-wire, two-element cell. A four-wire, four-elementcell 10 has electrodes 80, 82, 84, and 86. Electrodes 80 and 86 aredrive electrodes and receive the sine-wave excitation from winding 54.Electrode 80 is the DRIVE2 input and is connected to winding 54, whileelectrode 86 is the DRIVE1 input and is tied to ground to complete adrive circuit path through cell 10. Electrodes 82 and 84 are senseelectrodes to detect the voltage across and the current through cell 10.Electrode 82 is the SENSE2 electrode, while electrode 84 is the SENSE1electrode. Resistor 78 is connected between DRIVE2 electrode 80 andSENSE2 electrode 82, while resistor 88 is connected between SENSE1electrode 84 of cell 10 and ground. Resistors 78 and 88 preferably areof equal value and act to keep circuit parameters stable when cell 10 isdisconnected from the circuit.

In a typical four-wire, four-element cell, an excitation is applied todrive electrodes 80 and 86. Sense electrode 82 is positionedsufficiently close to drive electrode 80 so as to be substantially atthe same electrical potential as drive electrode 80. Similarly, senseelectrode 84 is positioned sufficiently close to drive electrode 86 soas to be substantially at the same electrical potential as driveelectrode 86. Sense electrodes 82 and 84 are preferably disposedsubstantially within the current flow path through the cell 10 betweendrive electrodes 80 and 86. In a typical four-wire, two-element cell,drive electrode 80 is electrically short-circuited to sense electrode82, and drive electrode 86 is electrically short-circuited to senseelectrode 84.

In operation, a complete circuit path is traversed from one side ofwinding 52, through one of the switches 60, 62, and 64, throughresistors 72, 74, and 76, to ground. From ground, the circuit pathcontinues to electrode 86 of cell 10, through cell 10 to electrode 80,then through winding 54 to the other side of winding 52, thus completingthe circuit path. The values of the range selection signals determinewhether one, two, or all three of resistors 72, 74, and 76 are in thecircuit path. Thus, it can be seen that, as shown in FIG. 5, the signalsource 14, reference resistance 12, and cell 10 form a series circuit.

Turning to FIG. 7b, the tie point of switch 64 and resistor 76 (FIG. 7a)is connected to the non-inverting input of op amp 100, while the tiepoint of switch 62 and resistors 74 and 76 (FIG. 7a) is connected to thenon-inverting input of op amp 102. Op amps 100 and 102 are unity-gainbuffer amplifiers that buffer the voltages XA, XB, respectively, fromthe reference resistors 72, 74, and 76 (FIG. 7a). The outputs of op amps100 and 102 are connected to inputs Y and X, respectively, of analogswitch 104B. Switch 104B is one of three switches, along with switches104A and 104C, contained in a single integrated circuit package. Apreferred analog switch that features low sine-wave distortion and lowcrosstalk between switches is the HC4053 triple 2-channel analogmultiplexer/demultiplexer made by SGS-Thomson Microelectronics.

From the microprocessor 26 (FIG. 5), a standard select signal, STD_SEL,is connected to input B of switch 104B. The value of STD_SEL determineswhich input, X or Y, is connected to output BO/I. When RANGE_1 is lowand switch 64 (FIG. 7a) is on, then STD_SEL is high, input Y isconnected to output BO/I, and reference resistance voltage XA is presentat output BO/I of switch 104B. When either RANGE_2 or RANGE_3 is low,then STD_SEL is low, input X is connected to output BO/I, and referenceresistance voltage XB is present at output BO/I of switch 104B.

The tie point of electrode 82 and resistor 78 (FIG. 7a) is connected,through series-limiting resistor 106, to the non-inverting input ofunity-gain buffer op amp 108. The tie point of electrode 84 and resistor88 is connected, through series-limiting resistor 110, to thenon-inverting input of unity-gain buffer op amp 112. The output of opamp 108 is connected to the inverting input of unity-gain differentialamplifier 114, while the output of op amp 112 is connected to thenon-inverting input of unity-gain differential amplifier 114.

In the preferred embodiment, differential amplifier 114 is a PrecisionMonolithics AMP-03 is used due to its high (70-80 dB) common-moderejection ratio (“CMRR”). The unity-gain differential amplifier 114eliminates common mode voltages from the cell sense potentials XC andXD. For low unknown resistances, the resistance in the lead wires goingto and from the cell 10 (FIG. 7a) may be sufficiently large relative tothe cell resistance so as to induce relatively large measurement errors.Using four lead wires to the cell, in combination with unity-gaindifferential amplifier 114, effectively eliminates lead wire resistanceas a source of measurement error.

The output of unity-gain differential amplifier 114 is connected toinput Y of switch 104A and input Y of switch 104C. Output BO/I of switch104B is connected to potentiometer 116, capacitor 118, and input X ofswitch 104C. The wiper arm of potentiometer 116 is connected to input Xof switch 104A. Potentiometer 116, capacitor 118, and resistor 120 forma low-frequency compensation circuit Potentiometer 116 may be adjustedto ensure that zero crossings are accurately detected for low frequencysine-wave excitations.

From the microprocessor 26 (FIG. 5), a phase select signal, PHASE_SEL,is connected to input C of switch 104C, and determines whether input Xor Y is connected to output CO/I of switch 104C. When the unknown cellresistance is high, PHASE_SEL is high, input Y of switch 104C isconnected to output CO/I so that the sampled cell voltage at the outputof differential amplifier 114 appears at output CO/I of switch 104C, andsynchronous rectification takes place with respect to the cell voltageto eliminate parallel capacitance effects. When the unknown cellresistance is low, PHASE_SEL is low, input X of switch 104C is connectedto output CO/I so that the sampled reference resistance voltage at theoutput BO/I of switch 104B appears at the output CO/I of switch 104C,and synchronous rectification takes place with respect to the referenceresistance voltage to eliminate series capacitance effects.

Also from the microprocessor 26 (FIG. 5), an amplitude select signal,AMPL_SEL, is connected to input A of switch 104A, and determines whetherinput X or Y is connected to output AO/I of switch 104A. When it isdesired to integrate the sampled reference resistance voltage, thenAMPL_SEL is low, input X of switch 104A is connected to output AO/I, andthe sampled reference resistance voltage at output BO/I of switch 104Bis present at output AO/I of switch 104A. When it is desired tointegrate the sampled cell voltage, then AMPL_SEL is high, input Y ofswitch 104A is connected to output AO/I, and the sampled cell voltage atthe output of differential amplifier 114 is present at output AO/I ofswitch 104A

Output CO/I of switch 104C is connected to capacitor 122. Capacitor 122is a DC blocking capacitor that couples the sampled voltage which is tobe used as the phase synchronization reference to resistor 124 and thenon-inverting input of op amp 126. Op amp 126 is a unity-gain bufferamplifier that couples the signal to potentiometer 128 and capacitor130. Potentiometer 128 is in turn connected to resistor 132. The signalis then coupled from resistor 132 to the inverting input of op amp 134,back-to-back diode 136, and capacitor 138.

Capacitor 130 is further connected to back-to-back diodes 136 and 140.Back-to-back diode 140 is then connected to resistors 142 and 144. Theother lead of resistor 142 is tied to V_(EE), the negative supplyvoltage. The other lead of resistor 144 is connected to the output of opamp 134 and capacitor 138. The non-inverting input of op amp 134 is tiedto ground. The output of op amp 134 is further connected toseries-limiting resistor 146. Series-limiting resistor 146 couples theoutput from op amp 134 to the base of transistor 148. Transistor 148 isan NPN-type transistor with input to the base, emitter tied to ground,and output at the collector. The output at the collector is an invertedand amplified version of the signal input to the base. The collector oftransistor 148 is connected to resistors 150, 152, and 154. The otherlead of resistor 150 is tied to V_(CC), the positive supply voltage, andprovides collector current to transistor 148. The output of transistor148 is the zero-crossing signal PHASE_I. PHASE_I is a square wave signalin phase with the sine-wave input to the zero-crossing detector 22 (FIG.5) and has amplitude from about zero Volts to about five Volts.

Capacitors 122, 130, and 138, resistors 124, 128, 132, 144, 142, 146,150, 152, and 154, op amps 126 and 134, back-to-back diodes 136 and 140,and transistor 148 collectively comprise the zero-crossing detector 22(FIG. 5). In the preferred embodiment, the op amps 126 and 134 areMC34182 op amps, the back-to-back diodes 136 and 140 are MMBD7000Ldiodes, and transistor 148 is an MMBT3904LT1 general-purpose NPN silicontransistor, all manufactured by Motorola, Inc.

The signal that supplies the reference phase is coupled into thedetector 22 (FIG. 5) through blocking capacitor 122 and buffer op amp126. The input to detector 22 is typically a sine-wave voltage of fromabout 50 m V_(RMS) to about 2.0 V_(RMS). The signal is then coupledthrough potentiometer 128 and resistor 132 to the inverting input of opamp 134. The signal level at the inverting input of op amp 134 iscompared to the ground level at the non-inverting input of op amp 134and the difference is amplified. Because of the large open-loop gain ofop amp 134, the output of op amp 134 is driven toward V_(CC) when theinput signal is negative, and toward V_(EE) when the input signal ispositive. Thus, for a sine-wave input, the output of op amp 134 is aninverted square wave.

Resistors 142 and 144 provide the proper DC level at the output of opamp 134 and proper DC bias for back-to-back diodes 136 and 140. Toprevent op amp 134 from being driven into saturation, back-to-backdiodes 136 and 140 provide feedback from the output of op amp 134 to theinverting input of op amp 134 so as to cause op amp 134 to operate incurrent mode, thereby limiting the gain of op amp 134. The values ofresistors 142 and 144 preferably are such that the output of op amp 134is a square wave of amplitude from about −0.5V to about +1.5V withmidpoint about equal to the forward conductance voltage V_(BE) oftransistor 148.

Capacitor 138 provides feedback from the output of op amp 134 to theinverting input of op amp 134 to ensure more stable switching of the opamp 134 output for input voltage levels substantially equal to zerovolts by damping high-frequency oscillations at the output of op amp134. Capacitor 130 provides a small amount of leading phase angle tocompensate for a small amount of lagging phase angle induced byoff-state capacitance of the back-to-back diodes 136 and 140. Resistor132 provides series current limiting of the input signal to op amp 134while potentiometer 128 provides a means for compensating the phaseangle of high-frequency input signals for small zero-crossing detectionerrors.

Output AO/I of switch 104A is connected to the non-inverting input ofunity-gain buffer op amp 156. The output of op amp 156 is connected toresistor 158 and input Y of analog switch 160B. In the preferredembodiment, switch 160B is one switch of an HC4053 triple 2-channelanalog multiplexer/demultiplexer manufactured by SGS-ThomsonMicroelectronics. Op amp 162, resistors 158, 164, and 166 comprise aunity-gain inverting amplifier such that the voltage waveform at theoutput of op amp 162 is a mirror-image of the voltage waveform at theoutput of op amp 156. Preferably, resistors 158 and 164 are precisionresistors of equal value, and resistor 166 has value approximately halfthat of resistors 158 and 164. The output of op amp 162 is connected toinput X of switch 160B. The output of transistor 148 is coupled throughseries-limiting resistor 152 to input B of switch 160B.

Input B of switch 160B determines whether input X or input Y isconnected to output BO/I. When the input to zero-crossing detector 22(FIG. 5) is positive, PHASE_I is high, input Y of switch 160B isconnected to output BO/I, and the non-inverted version of the inputvoltage to the synchronous rectifier 18 (FIG. 5) is present at theoutput BO/I of switch 160B. When the input to zero-crossing detector 22is negative, PHASE_I is low, input X of switch 160B is connected tooutput BO/I, and the inverted version of the input voltage to thesynchronous rectifier 18 is present at the output BO/I of switch 160B.

Output BO/I of switch 160B is connected to a switch-capacitor low-passfilter comprised of resistor 168 and capacitors 170 and 172. Capacitor170 is connected to input Y of switch 160A, and capacitor 172 isconnected to input X of switch 160A. Amplitude signal select lineAMPL_SEL, from the microprocessor 26 (FIG. 5), is connected to input Aof switch 160A. The signal AMPL_SEL determines whether capacitor 170 or172 is connected to ground through output AO/I of switch 160A. WhenAMPL_SEL is low, input X of switch 160A is connected to output AO/I, andcapacitor 172 is connected to ground. When AMPL_SEL is high, input Y ofswitch 160A is connected to output AO/I, and capacitor 170 is connectedto ground. Thus, capacitor 170 is switched into the low-pass filter whenthe synchronously-rectified sampled cell voltage is being integrated,and capacitor 172 is switched into the low-pass filter when thesynchronously-rectified sampled reference resistance voltage is beingintegrated. Using two separate capacitors 170 and 172 for filtering theoutput of synchronous rectifier 18 permits faster switching betweeninput signals to the integrator 24 (FIG. 5).

The BO/I output of switch 160B passes through resistor 168 to the VIN+input of integrating analog-to-digital converter 174 (FIG. 7c).Analog-to-digital converter 174, in the preferred embodiment, is aTC500A integrating converter analog processor manufactured by TeledyneComponents. Converter 174 is a microprocessor-controlled dual-slopeintegrating converter. Capacitor 176 and resistors 178 and 180 provide areference voltage to input REFH of converter 174. The reference voltageof the preferred embodiment is about 200 mV, but the absolute value isnot critical so long as the voltage remains stable from one conversionto the next. Inputs REFL and ACOM are tied to ground. Connected to inputBUF is resistor 182. Capacitor 184 is connected to input CAZ andcapacitor 186 is connected to input CINT. The other ends of resistor 182and capacitors 184 and 186 are tied together. Capacitor 188 is connectedbetween inputs CREF+ and CREF−. From the microprocessor 26 (FIG. 5), twocontrol signals, A and B, are connected to inputs A and B, respectively.The output of the converter 174 appears at output COUT as output signalCOMP.

When the control signals AB to converter 174 are set to 01, converter174 is in its resting state (i.e. not converting). On instruction fromthe microprocessor 26, control signals AB are set to 10 to begin theintegration process. Integration is set to begin and end on zerocrossings detected by the zero-crossing detector 22 (FIG. 5), with aminimum integration time as determined by the microprocessor 26 suchthat an even number of half-cycles will always be integrated.Integrating over an even number of half-cycles helps to eliminate errordue to possible DC levels present in the signal to be integrated. Also,to enhance resolution of low voltage signals, the integration time maybe lengthened. During the signal integration period, the microprocessor26 counts the number of microprocessor clock cycles to determine theactual integration time.

At the end of the signal integration period, microprocessor 26 setscontrol signals AB to 11 to start deintegration. Converter 174 thenintegrates the reference voltage at input REFH so as to drive the outputat COUT back toward zero. The microprocessor 26 counts microprocessorclock cycles during the deintegration period. When the COMP outputsignal goes low, deintegration is complete, and the microprocessor 26sets control signals AB to 01 to zero the converter 174 COMP outputuntil the next conversion period.

The microprocessor 26 then uses the integration time, deintegrationtime, and known reference voltage to compute a DC voltage value for thesignal voltage applied to the converter 174 VIN+ input during theintegration time period. The larger the input voltage to converter 174is relative to the reference voltage at VREF+, the longer it takes todeintegrate the COMP output back to a low level. The computed DC voltagevalue represents the RMS voltage value for the input voltage and iscomputed by multiplying the known reference voltage times the ratio ofthe deintegration time to the integration time.

Turning now to FIG. 8, a conductivity meter incorporating the preferredembodiment of the invention can be seen. Microprocessor 26 is connectedto a keypad 202 and buzzer 204 through keypad controller 206. Anoperator can enter information into the meter and select different modesof operation through keypad 202. The microprocessor 26 can generate atone from buzzer 204 when desired. Watchdog timer 208 monitorsmicroprocessor 26 and provides a reset signal to microprocessor 26 if nomicroprocessor 26 activity is detected for a predetermined interval oftime. Real time clock 210 provides external timing information tomicroprocessor 26. Microprocessor 26 is connected through serial portinterface 212 to an RS-232 port 214 to permit communication withexternal peripheral devices. Programmable read-only memory (“ROM”) 216contains the software instructions which control the operation of themeter and are executed by microprocessor 26. Random-access memory(“RAM”) 218 is used by microprocessor 26 to store informationMicroprocessor 26 addresses ROM 216 and RAM 218 via address bus 220.Data is communicated among the microprocessor 26, ROM 216, RAM 218,display 222, and data latch 224 via data bus 226. Display 222 ispreferably a liquid-crystal display, but may be any means suitable forvisually displaying information. Data latch 224 holds the variouscontrol signals used by the different parts of the meter.

Microprocessor 26 controls the operation of sine-wave generator 30 toproduce sine-wave excitation of predetermined frequency and amplitude.Sine-wave excitation is coupled by means of switches 64, 62, and 60, inresponse to range select signals RANGE_1, RANGE_2, and RANGE_3,respectively, from data latch 224, to reference resistors 76, 74, and72. Sine-wave excitation is also coupled from sine-wave generator 30 tocell 10. Range select signal RANGE_1 is also coupled to platinizingcircuit 226, which is coupled to cell 10 via switch 228 in response to aplatinizing signal PLAT from data latch 224. Platinizing circuit 226provides a reversible 30 mA current to cell 10 to permit deposition ofplatinum black on the cell electrodes (not shown).

In response to standard select signal STD_SEL from latch 224, switch104B provides the appropriate reference resistance sample voltage toswitches 104A and 104C. The sampled cell voltages from cell 10 areapplied to differential amplifier 114, then to switches 104A and 104C.In response to phase select signal PHASE_SEL from latch 224, switch 104Cpasses the appropriate sample voltage to zero-crossing detector 22. Thezero-crossing detector 22 output signal PHASE_I is provided tomicroprocessor 26 and synchronous rectifier 18.

In response to amplitude select signal AMPL_SEL, switch 104A passes theappropriate sample voltage to synchronous rectifier 18. Thesynchronously-rectified output from rectifier 18 is coupled to theswitched-capacitor low-pass filter comprised of resistor 168 andcapacitors 170 and 172. The appropriate capacitor 170 or 172 isconnected to ground by switch 160A in response to signal AMPL_SEL fromlatch 224.

Cell 10 may contain a built-in thermistor (not shown) which provides anoutput through external thermistor jack 230 to switch 160C. Temperatureinformation from the built-in thermistor, or alternatively from anexternal thermistor (not shown), is coupled from jack 230 to switch 160.In response to a signal A/D_SEL from latch 224, switch 160 passes eithera synchronously-rectified sample voltage or a thermistor voltage tointegrator 24. The output from integrator 24 is provided tomicroprocessor 26 for calculation of the appropriate parameters.

Although the present invention has been described with reference topreferred embodiments, it is to be understood that various modificationsmay be made without departing from the spirit and scope of theinvention. Moreover, the invention is not limited to the particular formor arrangement described herein except to the extent that suchlimitations are found in the claims.

What is claimed is:
 1. A method of compensating for unknown parallel capacitance during measurement of the resistivity of a liquid, comprising the steps of: (1) placing said liquid in communication with a pair of cell electrodes; (2) placing a reference resistance in series with said cell electrodes; (3) connecting a periodic, alternating electrical drive potential across the series combination of said cell electrodes and said reference resistance; (4) measuring a potential difference across said cell electrodes; (5) determining a first crossover time at which said potential difference across said cell electrodes undergoes a first change of sign between a negative and a positive value; (6) determining a second crossover time when said potential difference across said cell electrodes undergoes another change of sign between a negative and a positive value; (7) measuring a potential difference across said reference resistance; (8) generating a reference integrand by integrating said potential difference across said reference resistance for a time period extending from said first crossover time to said second crossover time; (9) generating a cell integrand by integrating said potential difference across said cell for a time period extending from said first crossover time to said second crossover time; (10) calculating a ratio between said cell integrand and said reference integrand; and (11) multiplying said ratio by said reference resistance.
 2. A method according to claim 1 wherein said periodic, alternating electrical drive potential is a sine wave.
 3. A method according to claim 1 wherein said potential difference across said cell electrodes is rectified prior to integration thereof.
 4. A method according to claim 1 wherein said potential difference across said reference resistance is rectified synchronously with respect to said potential difference across said cell electrodes prior to integration thereof.
 5. A method of compensating for unknown series capacitance during measurement of the resistivity of a liquid, comprising the steps of: (1) placing said liquid in communication with a pair of cell electrodes; (2) placing a reference resistance in series with said cell electrodes; (3) connecting a periodic, alternating electrical drive potential across the series combination of said cell electrodes and said reference resistance; (4) measuring a potential difference across said reference resistance; (5) determining a first crossover time at which said potential difference across said reference resistance undergoes a first change of sign between a negative and a positive value; (6) determining a second crossover time when said potential difference across said reference resistance undergoes another change of sign between a negative and a positive value; (7) measuring a potential difference across said cell electrodes; (8) generating a reference integrand by integrating said potential difference across said reference resistance for a time period extending from said first crossover time to said second crossover time; (9) generating a cell integrand by integrating said potential difference across said cell for a time period extending from said first crossover time to said second crossover time; (10) calculating a ratio between said cell integrand and said reference integrand; and (11) multiplying said ratio by said reference resistance.
 6. A method according to claim 5 wherein said periodic, alternating electrical drive potential is a sine wave.
 7. A method according to claim 5 wherein said potential difference across said cell electrodes is rectified prior to integration thereof.
 8. A method according to claim 5 wherein said potential difference across said reference resistance is rectified synchronously with respect to said potential difference across said cell electrodes prior to integration thereof.
 9. Apparatus for measuring the resistivity of a liquid, said apparatus comprising: (a) a pair of cell electrodes for contacting said liquid; (b) a reference resistance connected in series with said cell electrodes; (c) a driver for generating a periodic alternating drive signal and applying said drive signal to the series combination of said cell electrodes and said reference resistance; (d) a sample selector for selectively generating either a cell sample signal or a reference resistance sample signal, said cell sample signal indicating the voltage across said cell electrodes and said reference resistance sample signal indicating the voltage across said reference resistance; (e) a phase detector for selectively detecting either a cell phase indicating the phase of said cell sample signal or a reference resistance phase indicating the phase of said reference resistance sample signal; (f) a synchronous rectifier for selectively rectifying either said reference resistance sample signal and said cell sample signal synchronously with respect to the phase of the reference resistance sample signal or, alternatively, rectifying said reference resistance sample signal and said cell sample signal synchronously with respect to the phase of said cell sample signal; (g) an integrator for generating a first cell integrand by integrating said cell sample signal, a second cell integrand by integrating said synchronously rectified cell signal, a first reference resistance integrand by integrating said rectified reference resistance signal and a second reference resistance integrand by integrating said synchronously rectified reference resistance signal; and (h) a microprocessor for controlling the operation of said sample selector and said synchronous rectifier, said microprocessor also being programmed to calculate a resistivity value selectively compensated for unknown parallel capacitance by multiplying said reference resistance against a first ratio or alternatively compensated for an unknown series capacitance by multiplying said reference resistance against a second ratio, said first ratio being the ratio of said first cell integrand to said second reference resistance integrand, said second ratio being the ratio of said second cell integrand to said first reference resistance integrand. 